The present invention relates to electronic circuits, and more particularly to phase-locked loops.
Phase-locked loops (PLLs) are used in a wide variety of electronic devices to produce an output signal that is phase-aligned with a reference signal. One common use of PLLs is to generate an output frequency that is a rational multiple of the reference frequency, according to the equation fout=M/N*fref. Prior PLLs accomplish this by dividing the reference signal fref by M before the reference signal is passed to a phase frequency detector, and dividing a feedback signal within the PLL by N before the feedback signal is passed to the phase frequency detector.
Unfortunately, this approach removes M-1 of M of the reference clock edges leading to the phase frequency detector, eliminating most of the information used to keep the PLL tracking properly. This causes the PLL to make fewer, larger corrections in order to keep the output signal locked to the reference signal, resulting in undesirable tracking jitter in the output signal. This is particularly the case where N and M are large values, such as in high-speed applications requiring extremely precise phase alignment of the output signal to the reference signal. Since PLLs are often used to output clock signals that drive a variety of other devices, any long-term or tracking jitter in the output signal may have disastrous effects for the performance of the system overall.
It would be desirable to provide a PLL with decreased tracking jitter, to overcome the problems associated with the prior art.
A phase-locked loop system and method are provided. According to one aspect of the invention, the system typically includes an error detector configured to receive a reference signal, and a voltage-controlled oscillator subsystem coupled to the error detector. The voltage-controlled oscillator subsystem is typically configured to produce a primary output signal that tends toward a predefined frequency relationship with the reference signal, and to produce a feedback signal that is routed in a feedback loop back to the error detector. The voltage-controlled oscillator subsystem typically includes a multiple output voltage-controlled oscillator having a plurality of VCO outputs. The voltage-controlled oscillator subsystem is typically configured to form the feedback signal from a plurality of the VCO outputs.
According to another aspect of the invention, the phase-locked loop system includes an error detector configured to receive a reference signal, and a voltage-controlled oscillator subsystem configured to produce a primary output signal based on the reference signal, and to produce a feedback signal that is routed back to the error detector. The system may further include a correcting charge pump coupled to the output of the error detector. The correcting charge pump is typically configured to output a correcting pulse in response to a detected phase error between the reference signal and the feedback signal. The system may also include a canceling charge pump coupled to an output of the correcting charge pump. The canceling charge pump is typically configured to output a canceling pulse to compensate for at least a portion of the correcting pulse.
According to another aspect of the invention, the phase-locked loop method includes receiving a reference signal, and producing a primary output signal that tends toward a predefined frequency relationship with the reference signal. The method further typically includes generating a plurality of derivative signals based on the primary output signal, and producing a feedback signal based on the plurality of derivative signals.
According to another aspect of the invention, the phase-locked method includes receiving a reference signal and producing a primary output signal that tends toward a predefined frequency relationship with the reference signal. The method may further include producing a feedback signal that is based on the primary output signal and generating a correcting pulse in response to a detected phase error between the reference signal and the feedback signal. The method may also include generating a canceling pulse to compensate for at least a portion of the correcting pulse.